Incremental Design Debugging in a Logic Synthesis Environment

In today’s complex and challenging VLSI design process, multiple logic errors may occur due to the human factor and bugs in CAD tools. The designer often faces the challenge of correcting an erroneous design implementation. This study describes a simulation-based logic debugging solution for combinational circuits corrupted with multiple design errors. Unlike other simulation-based techniques that identify all errors at once, the proposed method works incrementally. At each iteration of incremental debugging, a single candidate location is rectified with linear time algorithms. This is done so that the functionality of the erroneous design gradually matches the correct one. A number of theorems, heuristics and data structures help identify a single candidate solution at each iteration and they also guide the search in the large solution space. Experiments on benchmark circuits confirm the effectiveness of incremental logic debugging. Andreas Veneris Jiang Brandon Liu University of Toronto Freescale Semiconductors Dept ECE and CS High Performance Tools Group Toronto, ON M5S 3G4 Austin, TX 78729 [email protected] [email protected]